This invention relates to radio frequency modulation and in particular to a radio frequency modem having an improved clock recovery circuit.
A radio frequency modem must receive data transmitted by another modem or by a head-end. Although the data transmission rate for a network is typically specified, slight differences in transmission rates may exist for many reasons including temperature variations and tolerances. In a network designed in accordance with IEEE specification 802.4, which is hereby incorporated by reference, the head-end is required to be the source of all data timing on the network.
It is desirable to sample received data at precise locations to assure accurate interpretation of the data. Since the clock within the receiving modem is not synchronized with the clock of the head-end or a transmitting modem, and since other factors such as temperature variations and tolerances make it impossible to solely use a clock in the receiving modem to determine precisely when to sample the incoming data, timing information used by a transmitting modem to send data must be recovered from data upon its receipt by a receiving modem.
Typical prior art clock recovery or timing recovery circuits employ a phase-locked loop having a voltage controlled oscillator. The input voltage to the voltage controlled oscillator is controlled as the difference between a voltage reference and another signal. Typically the voltage reference has been established using a voltage divider network or potentiometer and required compensation or adjustment for variations in temperature and other factors.
While the performance of clock recovery circuits having prior art voltage references have proven to be satisfactory, it is desirable to have a voltage reference that does not require adjustment or compensation for such variables as a change in temperature. Such a voltage reference would provide a clock recovery circuit yielding precise clock information.